(1) Field of the Invention
The present invention relates to a method of fabricating a non-volatile memory device, on a semiconductor substrate, and more specifically to a process used to create a metal contact to a control gate region, of the non-volatile memory device, and to use the same metal contact to create a metal-polysilicon capacitor structure, to increase control gate coupling capacitance.
(2) Description of the Prior Art
The semiconductor industry has been creating non-volatile memory devices, and memory cells, using a double polysilicon configuration. The first polysilicon layer is used as a floating gate, located overlying a thin insulator layer, that is used as the tunnel oxide of the non-volatile memory device. The second polysilicon layer is used for the control gate, with the second polysilicon layer also used as a wordline, sometimes traversing a long row of array devices. The high resistance of the long polysilicon line, compared to metal counterparts, can result in wordline RC time delays, adversely influencing device or cell performance, thus the trend to single polysilicon, non-volatile memory devices, became prevalent in the semiconductor industry. The single polysilicon, non-volatile memory device is comprised of a polysilicon floating gate structure, and a doped region in the semiconductor substrate, used for the control gate. However for performance considerations, the coupling capacitance of the single polysilicon, non-volatile memory device, has to be maximized. This is sometimes accomplished by increasing the dimensions of the control gate, or doped region in the semiconductor, however this design consumes more area than desired, adversely influencing chip density and cost.
This invention will offer a solution to the coupling capacitance concerns, inherent in conventional single polysilicon, non-volatile memory devices. A metal contact structure, is configured to serve as a direct contact to the control gate region, while also configured to be used as a top plate of a capacitor structure, comprised of the overlying metal contact structure, and dielectric layer which resides on the top surface of the underlying polysilicon floating gate structure. The metal contact configuration, described in this invention, increases the control gate coupling ratio, without increasing the dimension of the single polysilicon, non-volatile memory device, thus positively influencing device performance, without consuming additional area. Prior art, such as Logie, in U.S. Pat. No. 4,924,278, and Chang, in U.S. Pat. No. 5,761,121, describe a process for fabricating a single polysilicon, non-volatile memory device, however these prior arts do not disclose the use of a metal contact structure, to a control gate region, in the semiconductor substrate, and also used as a component of a capacitor structure, used to increase the coupling capacitance of the device.